In recent years in an application circuit such as a PWM inverter, a synchronous commutation down-converter, and a class-D amplifier, a level shift circuit, by means of a high-voltage integrated circuit, has been used as a circuit for driving a high potential side switching device in two switching devices connected in series between high and low potentials.
A level shift circuit of this kind has a configuration such that, in order to reduce power consumption, only when signal switching occurs between externally supplied command signals that are used to render a semiconductor switching device on the high potential side conductive or non-conductive, a short ON or OFF pulse on the order of a few hundreds of nanoseconds is generated and the generated pulse is transmitted to the switching device drive circuit on the high potential side, where a latch circuit latches the switching device in its ON or OFF state.
In such a level shift circuit, a VS potential, which is a reference voltage of the high potential side switching device, varies with a conduction/non-conduction of the switching device, resulting in application of a greater voltage variation dV/dt to the level shift circuit. This causes in some cases an unintended ON/OFF pulse (error pulse). In this regards, there exists a level shift circuit that includes a signal disabling circuit that prevents generation of the error pulse so that the high potential side switching device may not malfunction even in such cases (refer, for instance, to Japanese Unexamined Patent Application Publication 2000-252809, which is hereinafter called Patent document 1).
In the signal disabling circuit disclosed in Patent document 1, an output signal from an ON pulse section in the level shift circuit, is masked by an output signal from an OFF pulse section in the level shift circuit, while the output signal from the OFF pulse section in the level shift circuit is in turn masked by the output signal from the ON pulse section in the level shift circuit. Because the error pulses due to the application of the variation dV/dt occur basically simultaneously on both ON and OFF pulse sections in the level shift circuit, such a circuit configuration makes it possible to discriminate between a normal signal and an error signal to thereby nullify the error signal only.
However, because of variation in logic threshold values and/or load resistances within the level shift circuit, and because of the influence of wiring impedance, the error pulses—which would normally occur simultaneously on both ON and OFF pulse sections in the level shift circuit—are in some situations generated with some phase difference.
To this end, in Patent document 1, a level shift circuit is disclosed which, by fully masking a pulse width of the normal signal using that of a masking signal, does not malfunction even though error pulses with the phase difference are generated.
However, there is a problem to be overcome in the level shift circuit according to Patent document 1 described above, as will be described below.
In order for the masking pulse width to fully mask the pulse width of the normal signal, a threshold value of a NOT circuit for masking needs to be made smaller than that of the normal signal. This difference between the threshold values represents the difference between the pulse width of the normal signal and that for the masking. Thus, the difference between both widths is preferably made greater in order to achieve reliable masking. The NOT circuit generally uses an N-MOS transistor and a P-MOS transistor that are connected in series together, and a ratio of both transistor sizes is adjusted in order to obtain a desired threshold value.
However, if the threshold value is to be reduced without impairing drive capability of the masking NOT circuit, then the size of the P-MOS transistor needs to be increased. For that reason, the threshold value of the masking NOT circuit cannot be made much smaller because of area constraints of the IC chip, thus imposing a limit on the capability of removing the error pulses with the phase difference.
Further, while it is disclosed that a comparator with a different reference voltage is used in place of the NOT circuit, and that different delay circuits are applied individually to the normal signal and the masking signal to thereby reduce or increase the pulse width, a problem is created in that any of these disclosed techniques makes the total circuit more complex, thus resulting in an increased IC chip size.